Version 1.16

New minor release, created on 17th June 2025. Milestone: Release 1.16

Tested mainly with Vivado 2020.2 and 2022.2.

Contains Ethernet-based example designs for:

• Xilinx KC705 eval board

• Xilinx KCU105 eval board

• Xilinx VCU118 eval board

• Xilinx ZCU102 eval board

• PC053a

And PCIe-based example designs for:

• HiTech Global K800

• Xilinx VCU118 eval board

Core

Improvements

• Add dependency files for wider range of packages & entities [issue #246]

Slaves and utilities

Improvements

• Add dependency files for wider range of packages & entities [issue #246]

• ipbus_axi4lite_master: Updated to support configurable AXI4 bus width (incl. address table changes) [issue #245]