Version 1.10

New minor release, created on 7th Sept 2021. Milestone: milestone #11

Tested mainly with Vivado 2019.2 and 2020.2.

Contains Ethernet-based example designs for:

  • Xilinx KC705 eval board

  • Xilinx KCU105 eval board

  • Xilinx VCU118 eval board

  • Xilinx ZCU102 eval board

  • PC053a

And PCIe-based example designs for:

  • HiTech Global K800

  • Xilinx VCU118 eval board

Core

Bugfixes

  • AXI transport interface (ipbus_transport_axi): Simulation dep files fixed [issue #198]

Boards, example designs and utilities

  • Standardise the clock constraints across example designs, taking into account [issue #107]

Backward-incompatible changes

  • Exposed rarp_enable signal on ethernet example infra blocks [PRs #197 and #200]

  • Enclustra boards moved to the ipbus-contrib GitHub organisation [PR #187]