Version 1.2

New minor release, created on 24th May 2018. Milestone: Release 1.2

Tested mainly with Vivado 2016.4 to 2017.4; contains example designs for:

  • Enclustra AX3 module, using the RGMII PHY on the PM3 baseboard

  • Xilinx KC705 eval board

  • Xilinx KCU105 eval board

  • PC053a

License: IPbus firmware is now released under the Apache 2.0 license - a permissive license that allows the firmware to be used for any purpose, and allows the source code to be modified provided that the original license information and author attributions are not deleted.

Directory structure: The directories containing the main components have been reorganised as follows:

Old path

New path

components/ipbus/firmware/ethernet

components/ipbus_eth

components/ipbus/firmware/ipbus_core

components/ipbus_core

components/ipbus/firmware/slaves

components/ipbus_slaves

Core

Backward-incompatible changes

  • ipbus_ctrl: The 4 output ports starting with pkt_ have been replaced by 2 output ports, pkt and pkt_oob

  • transactor and transactor_if: Removed output ports pkt_rx and pkt_tx (corresponding pkt output port added to trans_arb)

  • stretcher: Superceeded by led_stretcher entity in ipbus_util

Additions

  • ipbus_dc_fabric_sel: Daisy-chain style fabric selector (use with corresponding new type from ipbus_package.vhd)

Bugfixes

  • ipbus_fabric_simple: Fixed typo in signal assignment [issue #35]

Slaves

The main ipbus_*reg slaves have been replaced by new slaves that allow you to easily instantiate either a single register, or a block of registers:

Superceeded by

ipbus_ctrlreg

ibpus_ctrlreg_v

ipbus_reg

ipbus_reg_v

ipbus_syncreg

ipbus_syncreg_v

Also, the slaves entity in slaves.vhd that is used for example designs has been replaced by ipbus_example in components/ipbus_util

New slaves

ipbus_ctrs_samp

Interface to block of external wide counters

ipbus_ctrs_v & ipbus_ctrs_ported

Block of counters, latter accessed like ported RAM

ipbus_ported_dpram

Generic 32b (or less) wide dual-port memory with ported IPbus access on one side

ipbus_ported_sdpram72

Generic 72b wide simple-dual-port memory with ported IPbus access on one port

ipbus_roreg_v

Block of read-only registers [issue #14]

ipbus_sdpram72

Generic 72b wide simple-dual-port memory with IPbus access on one port

uc_pipe_interface

uc_spi_interface

Other improvements

  • Changed types of various generics between natural and positive in several slaves

  • drp_decl package: Added constant DRP_WBUS_NULL

  • ipbus_ctrlreg_v, ipbus_reg_v and ipbus_syncreg_v: Added input port qmask with default value

  • syncreg_r and syncreg_w: Changed KEEP = TRUE signal attribute to SHREG_EXTRACT = no, and added attribute ASYNC_REG = yes [issue #5]

Bugfixes

  • ipbus_ctrlreg_v: Fixed bug that could cause strobe output signal to latch under some circumstances [issue #26]

  • ipbus_syncreg_v: Fixed bug that occasionally invalidated output data for read requests if N_CTRL = 0 [issue #11]

    • This bug also affected ipbus_ctrs_ported, that internally uses ipbus_syncreg_v with N_CTRL = 0

  • ipbus_syncreg_v: Fixed race condition that caused a lock-up condition if a block of syncreg_v stat registers were read too quickly [issue #34]

  • Ported RAM slaves: Fixed bug that, under some circumstances, could prevent pointer being updated for writes [issue #18]

Ethernet

Removed

  • eth_pcspma_basex_11_2.xco, gig_eth_pcs_pma_v11_*.xco, mac_fifo.xco and tri_mode_eth_mac_*.xco

  • eth_7s_1000basex_gth.vhd and eth_7s_1000basex_new.vhd

  • mac_bridge_*.vhd

New interfaces

eth_7s_1000basex_gtp.vhd

7 series. Instantiates the Xilinx MAC, 1000baseX pcs/pma & GTP transceiver cores

eth_7s_rgmii.vhd

7 series. Instantiates the Xilinx MAC & PHY interface for RGMII

eth_us_1000basex.vhd

Ultrascale. Instantiates the Xilinx MAC & 1000baseX pcs/pma & GTP transceiver cores

eth_rgmii.vhd

Other improvements

  • Simulation: Added support for custom virtual interfaces [issue #8]

  • eth_7s_1000basex: New input port sfp_los

  • eth_7s_gmii: Now uses temac_gbe_v9_0_gmii (previously used tri_mode_eth_mac_v5_4)