Version 1.11

New minor release, created on 11th May 2023. Milestone: Release 1.11

Tested mainly with Vivado 2019.2 and 2020.2.

Contains Ethernet-based example designs for:

  • Xilinx KC705 eval board

  • Xilinx KCU105 eval board

  • Xilinx VCU118 eval board

  • Xilinx ZCU102 eval board

  • PC053a

And PCIe-based example designs for:

  • HiTech Global K800

  • Xilinx VCU118 eval board

Core

Backward-incompatible changes

  • ipbus_ctrl: Added support for DHCP with static reservation in the DHCP server [issue #212]

    • Note: The IP address must be a static reservation in the DHCP server as the firmware does not implement DHCP renewal

    • Added generic DHCP_RARP (defaults to 0, i.e. RARP)

    • Replaced generic IPBUSPORT with port ipbus_port

    • Replaced port RARP_SELECT with port IPAM_SELECT (same function as before, but renamed to reflect that now can choose a different IPAM implementation)

    • Added 3 output ports: actual_mac_addr, actual_ip_addr and got_ip_addr

Improvements (backward-compatible)

  • PCIe interfaces (ipbus_pcie): Add CPLL-based version of the XDMA interface [issue #216]

  • PCIe interfaces (ipbus_pcie): Add support for setting PCI identifiers using generics [issue #204]

    • New generics: G_PCI_VENDOR_ID, G_PCI_DEVICE_ID, G_PCI_REVISION_ID, G_PCI_SUBSYSTEM_VENDOR_ID, G_PCI_SUBSYSTEM_ID (default values match existing hardcoded values).

Bugfixes

  • Updated IP checksum calculation to be compliant with RFC 1624 [issue #210]

Slaves

Improvements

  • Added ipbus_freq_ctr_adv - a new frequency measurement entity, which measures the frequency using a dedicated reference clock (since the IPbus clock isn’t always precise, e.g. if derived from the PCIe clock) [issue #219]

  • ipbus_syncreg_v: Added protections against race condition that manifests in rare circumstances (enabled by setting the ULTRA_SAFE generic to true) [issue #189]

Boards, example designs and utilities

Bugfixes

  • K800 (xdma bypass): Fixed build error (signal width mismatch) [issue #205]

  • VCU118 (SGMII): Fixed termination settings of clock pins [issue #211]