Version 1.8

New minor release, created on 29th April 2020. Milestone: Release 1.8

Tested mainly with Vivado 2018.3 and 2019.2. Contains Ethernet-based example designs for:

  • Enclustra AX3 module, using the RGMII PHY on the PM3 baseboard

  • Xilinx KC705 eval board

  • Xilinx KCU105 eval board

  • Xilinx VCU118 eval board

  • Xilinx ZCU102 eval board

  • PC053a

And PCIe-based example designs for:

  • HiTech Global K800

  • Xilinx VCU118 eval board

Core

Bugfixes

  • PCIe: Corrected minor syntax issue in ipbus_transport_multibuffer_if.vhd that Vivado flags as a critical warning [issue #164]

Slaves

New slaves

For Xilinx ICAP and IPROG primitives, and an IPbus slave that behaves as a master to AXI4-lite bus (courtesy of Jeroen Hegeman, all files under components/ipbus_util):

ipbus_icap_x7

ICAP (7-series devices) [issue #161]

ipbus_icap_us_usp

ICAP (Ultrascale & Ultrascale+) [issue #161]

ipbus_iprog_x7

IPROG (7-series devices) [issue #161]

ipbus_iprog_us_usp

IPROG (Ultrascale & Ultrascale+) [issue #161]

ipbus_axi4lite_master

Master to an AXI4lite bus [issue #168]

The ICAP slaves support register reads and writes, as well as FPGA reconfiguration from a configurable base address. The IPROG slaves support FPGA reconfiguration from a configurable base address.

Bugfixes

  • Added missing dependency to ipbus_freq_ctr.dep [issue #171]

  • Removed the id attribute from the root node of all address table files (since not used by uHAL) [issue #170]

Boards, example designs and utilities

Added a 7-series SGMII Ethernet block (tested on the VC707 development board) [issue #173]