Version 1.5

New minor release, created on 23rd August 2019. Milestone: Release 1.5

Tested mainly with Vivado 2017.4 and 2018.3. Contains Ethernet-based example designs for:

  • Enclustra AX3 module, using the RGMII PHY on the PM3 baseboard

  • Xilinx KC705 eval board

  • Xilinx KCU105 eval board

  • Xilinx VCU118 eval board (NEW in this release)

  • Xilinx ZCU102 eval board

  • PC053a

And PCIe-based example designs for:

  • HiTech Global K800

  • Xilinx VCU118 eval board

Core

The address width in the transactor interface (ipbus_trans_decl.addr_width) has been increased from 12 to 16 [issue #117]. N.B. This change is backward compatible for users, provided that values of the address fields in ipbus_trans_decl.ipbus_trans_out are either not directly specified by users, or ipbus_trans_decl.addr_width is used when specifying the widths of connected user-defined signals/variables.

Slaves

Bugfixes:

  • ipbus_pipeline: Fixed compilation error in strobe signal assignment [issue #99]

  • ipbus_dpram and ipbus_ported_dpram: Removed ‘null range’ aggregate assignment statements that result in critical warnings in Vivado 2018.3 when DATA_WIDTH = 32 [issue #110]

  • ipbus_ctrs_ported: Fixed compilation errors that arose with non-default values of generics [issue #122]

Boards, example designs and utilities

Backward incompatible changes:

  • Removed GLIB-specific code from the repository (i.e. all files under boards/glib_v3 and components/glib_infra) [issue #123]

Bugfixes:

  • VCU118 PCIe design: Fixed failure in IPBB-based build (by moving clocks_usp_serdes.vhd under components/ipbus_util/firmware/hdl/clocks directory, alongside other clocks modules)

Improvements:

  • Added an SGMII Ethernet-based example design for the VCU118 [issue #121]

  • Updated implementations of example designs to improve consistency across different boards [issue #107]