Slaves¶

The IPbus firmware repository, contains a library of generic slaves that have been used in a wide range of designs. These slaves are listed below; each one can be found under components/ipbus_slaves/firmware/hdl

Registers¶

`ipbus_ctrlreg_v`	Bank of control / status registers of parameterized size (bus has only read access to ‘status’ registers, but read-write access to ‘control’ registers)
`ipbus_reg_v`	Bank of registers of parameterized size (bus has read & write access to all of them)
`ipbus_roreg_v`	Block of read-only registers (i.e. values specified at build time, e.g. for version numbers)
`ipbus_syncreg_v`	Bank of control / status registers with clock-domain crossing

Counters¶

`ipbus_ctrs_ported`	Block of counters, accessed like ported RAM
`ipbus_ctrs_samp`	Interface to block of externally-provided counters (values of all counters sampled on same clock cycle)
`ipbus_ctrs_v`	Block of counters

RAMs¶

The depth of each RAM slave is parameterised through the generic ADDR_WIDTH. The ‘ported’ RAM slaves have zero wait states; all other RAM slaves have one wait state.

`ipbus_dpram`	32b (or less) wide dual-port memory with IPbus access on one side
`ipbus_dpram36`	36b wide dual-port memory with IPbus access on one side
`ipbus_ported_dpram`	32b (or less) wide dual-port memory with ported IPbus access on one side
`ipbus_ported_dpram36`	36b wide dual-port memory with ported IPbus access on one side
`ipbus_ported_dpram72`	72b wide dual-port memory with ported IPbus access on one side
`ipbus_ported_sdpram72`	72b wide simple-dual-port memory with ported IPbus access on one side
`ipbus_sdpram72`	72b wide simple-dual-port memory with IPbus access on one side

Miscellaneous¶

`ipbus_ctr`	Bus cycle counter (for debugging)
`ipbus_drp_bridge`	Interface to Xilinx DRP slave (for access to MGT, MAC, etc)
`ipbus_emac_hostbus`
`ipbus_freq_ctr`	Generic clock frequency monitor
`ipbus_freq_ctr_adv`	Generic clock frequency monitor, using separate reference clock
`uc_pipe_interface`

We have also developed IPbus slaves that provide an interface to the Opencores SPI and I2C master cores - these can be found at:

components/opencores_spi/firmware/hdl/ipbus_spi.vhd
components/opencores_i2c/firmware/hdl/ipbus_i2c_master.vhd