Version 1.15

New minor release, created on 8th July 2024. Milestone: Release 1.15

Tested mainly with Vivado 2020.2 and 2022.2.

Contains Ethernet-based example designs for:

  • Xilinx KC705 eval board

  • Xilinx KCU105 eval board

  • Xilinx VCU118 eval board

  • Xilinx ZCU102 eval board

  • PC053a

And PCIe-based example designs for:

  • HiTech Global K800

  • Xilinx VCU118 eval board

Core

Bugfixes

  • UltraScale+ PCIe XDMA wrapper: Resolve ‘missing port’ warning [issue #237]

Slaves and utilities

Backward-incompatible changes

  • ipbus_sysmon_us,usp: Extended existing endpoint to provide interface to SYSMONs on all SLRs [issue #239]

  • Updated depfiles for 2024 releases of IPBB (specifically, added --usefor flag). [issue #241]

Improvements (backward-compatible)

  • CDC for resets: Added SHREG_EXTRACT attribute, according to Xilinx’s guidelines [issue #233]

  • ipbus_drp_bridge: Add support for DRP clock differing from IPbus clock [issue #236]

New additions

  • ipbus_clk_bridge: A CDC for the entire bus [issue #235]

Boards, example designs and utilities

Improvements

  • VCU118 SGMII example design: Add 125 and 300 MHz clocks in infrastructure entity’s port map; adjust VCO frequency [issue #234]