Version 1.7
===========

New minor release, created on 3rd February 2020. Milestone: :github-fw-milestone:`Release 1.7 <8>`

Tested mainly with Vivado 2018.3 and 2019.2. Contains Ethernet-based example designs for:

* Enclustra AX3 module, using the RGMII PHY on the PM3 baseboard
* Xilinx KC705 eval board
* Xilinx KCU105 eval board
* Xilinx VCU118 eval board
* Xilinx ZCU102 eval board
* PC053a

And PCIe-based example designs for:

* HiTech Global K800
* Xilinx VCU118 eval board


Core
----

**Improvements**

* Transactor arbiter removed from main dependency file for ``ipbus_core`` [:github-fw-issue:`140`]
* Ethernet/UDP transport interface: Added new depfile, ``ipbus_ctrl.dep`` under ``components/ipbus_util`` that references ``ipbus_ctrl.vhd`` and all its dependencies [:github-fw-issue:`140`]
* AXI transport interface (``ipbus_transport_axi``): Simulation testbench files removed from main dependency file [:github-fw-issue:`136`]

**Bugfixes**

* PCIe: Resolved error during XDMA IP core upgrade that affected Ultrascale+ designs in Vivado 2019.2 [:github-fw-issue:`156`]

  * The new Ultrascale+ XDMA XCI file works with Vivado 2018.1 onwards


Slaves
------

**New slaves**

For Xilinx SYSMON and DNA primitives (all files under ``components/ipbus_util``):

.. table::
  :align: center

  ===========================  ==============================================================================================
  ``ipbus_sysmon_x7``          SYSMON (7-series devices) [:github-fw-issue:`144`]
  ``ipbus_sysmon_us``          SYSMON (Ultrascale devices) [:github-fw-issue:`144`]
  ``ipbus_sysmon_usp``         SYSMON (Ultrascale+ devices) [:github-fw-issue:`144`]
  ``ipbus_device_dna_us_usp``  DNA (Ultrascale & Ultrascale+) [:github-fw-issue:`151`]
  ===========================  ==============================================================================================


**Other improvements**

* Added dependency files for all slaves that have more dependencies than just the ``ipbus`` package [:github-fw-issue:`142`]. Specifically:

  * ``ipbus_ctrlreg_v``
  * ``ipbus_drp_bridge``
  * ``ipbus_emac_hostbus``
  * ``ipbus_reg_v``
  * ``ipbus_roreg_v``


**Backward-incompatible changes**

* ``ipbus_syncreg_v``: Renamed dependency file from ``syncreg_v.dep`` to ``ipbus_syncreg_v.dep`` (for consistency with other slave dependency files) [:github-fw-issue:`141`]
* ``freq_ctr_div``: Renamed VHDL file from ``ipbus_freq_ctr_div.vhd`` to ``freq_ctr_div.vhd`` [:github-fw-issue:`109`]
* ``drp_decl``: Increased address width from 9 to 16 bits [:github-fw-issue:`150`]
* ``ipbus_oob_test``: Removed, since no longer used [:github-fw-issue:`148`]


Boards, example designs and utilities
-------------------------------------

Added a preliminary implementation of an example design in which packets of IPbus transactions are sent and received over the PS-PL interface, as well as over an AXI chip-to-chip link. Board: ZCU102 [:github-fw-issue:`133`]

**Backward-incompatible changes**

* ``trans_buffer`` and ``trans_buffer_test``: Moved from ``components/ipbus_slaves`` to ``components/ipbus_util`` (since not a slave) [:github-fw-issue:`148`]

**Bugfixes**

* Fixed problems in simulation dependency files for a few example designs [:github-fw-issue:`154`]