Version 1.6
===========

New minor release, created on 22nd October 2019. Milestone: :github-fw-milestone:`Release 1.6 <7>`

Tested mainly with Vivado 2017.4 and 2018.3. Contains Ethernet-based example designs for:

* Enclustra AX3 module, using the RGMII PHY on the PM3 baseboard
* Xilinx KC705 eval board
* Xilinx KCU105 eval board
* Xilinx VCU118 eval board (**NEW in this release**)
* Xilinx ZCU102 eval board
* PC053a

And PCIe-based example designs for:

* HiTech Global K800
* Xilinx VCU118 eval board


Core 
----

No changes.


Slaves
------

No changes.


Boards, example designs and utilities
-------------------------------------

Bugfixes:

* Example designs: Fixed masks of ``led`` register (was ``0x3``, corrected to ``0x4``) [:github-fw-issue:`130`]
* Ultrascale(+) clock modules (``clocks_us_serdes`` and ``clocks_usp_serdes``): Updated logic to set aux-clock-domain reset signal(``rst_aux``) from post-buffer aux clock [:github-fw-issue:`128`]
* 7-series and Ultrascale(+) clock modules: Changed value of MMCM ``clkin1_period`` generic (``1000.0 / CLK_FR_FREQ``); values was previously ``CLK_VCO_FREQ / CLK_FR_FREQ`` which led to correct value for default value of ``CLK_VCO_FREQ`` generic. [:github-fw-issue:`127`]