Version 1.3
===========

New minor release, created on 20th Dec 2018. Milestone: :github-fw-milestone:`Release 1.3 <3>`

Tested mainly with Vivado 2016.4, 2017.4 and 2018.2. Contains example designs for:

* Enclustra AX3 module, using the RGMII PHY on the PM3 baseboard
* Xilinx KC705 eval board
* Xilinx KCU105 eval board
* Xilinx ZCU102 eval board
* PC053a


.. 
  Core
  ----

  **Backward-incompatible changes**

  **Additions**

  **Bugfixes**



Slaves
------

**New slaves**

.. table::
  :align: center
  :widths: 25 75

  ========================  ==============================================================================================
  ``ipbus_freq_ctr``        Generic clock frequency monitor [:github-fw-issue:`67`]
  ``ipbus_ported_dpram72``  Generic 72b wide dual-port memory with ported IPbus access on one side [:github-fw-issue:`82`]
  ========================  ==============================================================================================


**Other improvements**

* ``ipbus_ctrs_ported`` and ``ipbus_ctrs_v``: Initial values can now be written from IPbus, if wanted [:github-fw-issue:`64`]

  * The ability to write values is controlled through a new boolean generic, ``READ_ONLY``, which has a default value of ``true`` (ensuring backward compatibility if this generic is not set).

**Bugfixes**

* ``ipbus_dpram``: Fixed bug arising from internal data width mismatch [:github-fw-issue:`59`]
* ``ipbus_dpram36``, ``ipbus_sdpram72`` and ``ipbus_ported_sdpram72``: Fixed implementation so that RAMs are inferred as block RAMs (previously could be interferred as distributed RAMs) [:github-fw-issue:`81`]


Boards, example designs and utilities
-------------------------------------

**Backward-incompatible changes**

* All example designs: Updated to instantiate entity named ``payload`` rather than ``ipbus_example``, in order to simplify the re-use of ``infra`` and top-level entities with other payloads [:github-fw-issue:`17`]
* KCU105 infrastructure: Frequency of aux clock is now configurable through a new generic, ``CLK_AUX_FREQ`` [:github-fw-issue:`57`]

  * As part of this change, in ``clock_us_serdes`` we renamed output port ``clko_p40`` to ``clko_aux``, and added two new generics, ``CLK_VCO_FREQ`` and ``CLK_AUX_FREQ``; the default values of the new generics reproduce the previous behaviour of this entity.

* Simulation infrastructure: Frequency of aux clock is now configurable through a new generic, ``CLK_AUX_FREQ`` [:github-fw-issue:`72`]

  * As part of this change, in ``clock_sim`` we renamed output port ``clko40`` to ``clko_aux``, and added one new generic, ``CLK_AUX_FREQ``, with default value of 40.0 to reproduce previous behaviour.

**Other improvements**

* Simulation example design: IP and MAC address can now be set through generics of top-level entity [:github-fw-issue:`51`]

**Bugfixes**

* KCU105: Fixed a clock constraint-related error encountered with more recent versions of Ethernet core (e.g. in Vivado 2017.4) [:github-fw-issue:`62`]
* Simulation infrastructure: Updated reset logic so that Ethernet block is not reset during a 'soft reset' [:github-fw-issue:`77`]


..
  Internal testing infrastructure
  -------------------------------

  * CI : Run syntax checks and simulation for every commit (rather than just pull requests) --- [:github-fw-issue:`53`]
  * Migrated automated tests to gitlab CI [:github-fw-issue:`73`]
  * Added tests of RAM slaves [:github-fw-issue:`81`]